The present invention relates to methods of and devices and systems for inter-integrated circuit, or I2C, addressing and, more particularly, to methods of and devices and systems for I2C addressing using I2C-capable devices having internal addressing registers instead of address input/output pins.
Inter-integrated circuit buses, also known as I2C buses and inter-IC buses, were developed in the early 1980's as simple, relatively short-distance, relatively low speed, low-bandwidth buses for communication on a common circuit board. The I2C bus is a bidirectional, two-wire bus used for serially-transmitting data between at least one master and at least one slave. These data include addressing data, which, by convention, commonly uses seven (7) bits. An eighth bit is included with the seven-bit address to tell the receiving node to read (transmit) or to write (receive).
A typical I2C system 10 having one master 12 and three slave nodes 14, 16, and 18 is shown schematically in FIG. 1. The two wires 11 and 13 of the I2C bus include a serial data line (SDA) and a serial clock line (SCL), respectively. Pull-up resistors 15, which are electrically-coupled to a voltage source (VDD) 19, are also provided for channel access. For example, pulling either of the two wires 11 and 13 to ground constitutes a logical low or zero (0), while allowing either of the lines to float constitutes a logical high or one (1).
The number of master devices and/or slave devices that is electrically-coupleable to the I2C bus, however, is limited, primarily, by the available addressing space. For example, if each device has a unique 7-bit address identifier code, there can be 27, or 128, unique and distinguishable devices electrically-coupleable to the I2C bus.
The proliferation and availability of I2C-capable devices and peripherals have resulted in the number of unique I2C-capable devices far exceeding the number of available addresses. Even extending the seven-bit addressing protocol to an extended, 10-bit protocol has failed to resolve the problem.
Dedicating or reserving some number of addresses is also common. Such “reserved addresses” that are set aside for special purposes cannot be otherwise used. Thus, with current I2C systems, a full seven-bit addressing range (or an extended 10-bit addressing range) is lacking.
To further exacerbate the problem of sufficient addressing space, I2C-capable devices or peripherals that are electrically-coupleable to an I2C bus, by design, dedicate a considerable if not significant portion of their available input/output (I/O) pins to device addressing. Referring to FIG. 2, there is shown a schematic of a conventional Texas Instruments power-source equipment (PSE) 20 having five I/O pins (labeled AD0 to AD4) dedicated exclusively for device addressing.
Accordingly, it would be desirable to provide means and methods for internally configuring the address identifier code of an I2C capable device or peripheral that can be electrically-coupled to an I2C bus without having to use addressing pins.